The present invention generally pertains to frequency synthesizers used in electronic communications and is particularly directed to an improvement in direct digital frequency synthesizers.
A direct digital frequency synthesizer generates an analog waveform of a predetermined frequency from accumulated digital frequency words which, as accumulated, represent the phase of a sine wave of said predetermined frequency. Referring to FIG. 1, a typical prior art direct digital frequency synthesizer includes a phase accumulator 10 for accumulating the digital frequency words 12 and a phase-to-magnitude converter 14 for converting the accumulated phase value 16 into an analog waveform 18 of the predetermined frequency. The phase-to-magnitude converter 14 includes a read-only memory (ROM) 20 and a linear digital-to-analog converter (DAC) 22 for converting the output 24 of the ROM 20 into the analog waveform 18. The ROM 20 converts the phase value accumulated in the phase accumulator 10 into a digital word 24, which when converted by the DAC 22, provides an analog signal magnitude for the phase angle of a sinusoidal waveform that is represented by the phase value in the phase accumulator 10. A clock 26 clocks the operations of the phase accumulator 10 and the phase-to-magnitude converter 14.
The phase accumulator 10 has a length of m bits and is driven at a clock rate f.sub.c by the clock 26. At each clock pulse, a frequency word 12 having a length of k bits is added to the present value in the accumulator 10. The value in the accumulator 10 increases at this rate until it overflows losing all bits that exceed 2.sup.m -1. The phase value in the accumulator 10 at any time represents the instantaneous phase angle of a sinusoidal waveform over a range of 2.pi. radians. This phase value is delivered to the ROM 20 in the form of an address to a lookup table implemented by the ROM 20 for conversion into a digital word 24 having a magnitude corresponding to the instantaneous sine value or magnitude.
The digital words provided by the ROM 20 are converted into the analog waveform 18 by the DAC 22. The finite number of magnitudes contained in the look-up table in the ROM 20 closely approximates the desired sinusoidal waveform magnitudes at the different phase values.
A low pass filter 28 is coupled to the output of the DAC 22 to reduce the resulting noise, spurious signals, and harmonics of the waveform 18 to acceptable levels, and thereby provides an analog output signal 30 at the frequency represented by the accumulated frequency words 12.
There are 2.sup.m different phase values; and the actual output frequency is g times f.sub.c /2.sup.m, where g can range from one to 2.sup.m. The frequency resolution is also equal to f.sub.c /2.sup.m, which means that the resolution requirements can generally be met by trading off f.sub.c and m. Since this is a sampled data system, it is not possible to provide a single output sine wave frequency in excess of 1/2 f.sub.c and exceeding 1/3 f.sub.c is considered the limit of practicality for the low pass filter 28.
The phase accumulator 10 performs a phase calculation once each clock cycle by adding the frequency word, which is proportional to the desired output frequency, to the contents of the accumulator 10.
It is not practically feasible (or necessary) to retain every bit from the phase accumulator 10; so the phase accumulator 10 is divided into a coarse accumulator and a fine-component accumulator. The full m bits are partitioned into c bits in the coarse-component accumulator and f bits in the fine-component accumulator. "C" and "f" are intergers. Only the c bits of the coarse-component accumulator are used to determine the phase value for one cycle of phase accumulator output, whereby phase resolution is limited to 2.pi./2.sup.c radians. Both the coarse-component accumulator and the fine-component accumulator are clocked by the clock 26 to run at a frequency of f.sub.c. The minimum frequency that the coarse-component accumulator can provide is f.sub.c /2.sup.c Hz. The fine-component accumulator provides finer frequency resolution by periodically adding a carry-in to the coarse-component accumulator's LSB of 2.pi./2.sup.c radian. Given that the fine-component accumulator consists of f bits and also runs at f.sub.c, the least carry-in rate it can provide is f.sub.c /2.sup.f. As each coarse LSB is worth 2.pi./2.sup.c radians, the minimum average frequency added by the low accumulator is 2.pi./2.sup.c times f.sub.c /2.sup.f radians/second or f.sub.c /2.sup.c+f Hz. Since m=c+f, the overall resolution, as weel as minimum step size remains unchanged by the separation.
Only the bits from the coarse-component accumulator (the c bits) are used to represent the necessary phase information with a resolution of 2.pi./2.sup.c radian. As the remaining fine-component accumulator bits (the f bits) of the accumulator are ignored by the ROM 20, tthe output phase function generally has a phase error with respect to the total phase function contained in the phase accumulator 10. Since there is no precise sine look-up table for a ROM, one can only approximate the sine look-up table, and as a result unwanted error spurs (spurious signals) occur. Furthermore, the phase error is slightly periodic in time, with the resultant effect of spurious lines or phase modulation (PM) spurs in the output spectrum.
The width (number of bits) of the DAC 22 determines the level of the amplitude spurs in the analog waveform 18 due to quantization of the digital to analog conversion, and the time skew between bit states results in glitch energy spurs. At higher specified clock rates, each of these factors can limit both the synthesizer maximum operating frequency and the output spurious level suppression. Since the DAC 22 cannot provide infinite amplitude resolution, periodic time errors occur which also appear in the output spectrum as discrete spurious lines. The fact that the DAC 22 cannot provide a perfect transfer function between its digital and its analog output results in various errors.
Errors that affect the output spectrum are integral linearity (N steps are N least significant LSB's), differential linearity (step to step in one LSB), nonmonotonic errors (one step goes the wrong way) and "glitch". All terms except "glitch", refer to semistatic errors and may be treated as an amplitude error.
Any real DAC introduces additional errors due to imprecise level control. However, as long as these errors are on the order of .+-.1/2 LSB as compared to an ideal value, the spurious level should be very nearly as predicted here.
The term `glitch` identifies a property of a DAC where the output does not proceed smoothly from one step to the next. Instead, due to the fact that all current switches within the DAC used to convert digital information to analog levels do not switch precisely at the same instant, a short spike of current is observed at the output at the transitive edge. The amount of glitch is expressed in units of volt sec., which gives a figure of merit for comparing different DAC's. This value ranges between 2.5 and 25 pico volt sec. for a prior-art 8-bit DAC.
Since the glitch event time is short, to block them from reaching the output, a sample and hold is sometimes added to the output prior to the low-pass filter. Another method is to follow the DAC with an operational amplifier that cannot follow the glitch due to slew rate limitations.
In order to suppress the phase and amplitude spurs to less than -70 dBc a 12-bit coarse-component accumulator and an 11-bit DAC is required.